aarch64-cpu

aarch64-cpu

Low level access to processors using the AArch64 execution state.

This project is developed and maintained by the Cortex-A team.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on current stable Rust. It might compile with older versions but that may change in any new patch release.

Usage

Please note that for using this crate's register definitions (as provided by aarch64_cpu::registers::*), you need to also import aarch64_cpu::registers::{Readable, Writeable}.

Example

Check out https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials for usage examples. Listed below is a snippet of rust-raspberrypi-OS-tutorials's early boot code.

use aarch64_cpu::{asm, registers::*};

// Some parts omitted for brevity.

unsafe fn prepare_el2_to_el1_transition(
    virt_boot_core_stack_end_exclusive_addr: u64,
    virt_kernel_init_addr: u64,
) {
    // Enable timer counter registers for EL1.
    CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);

    // No offset for reading the counters.
    CNTVOFF_EL2.set(0);

    // Set EL1 execution state to AArch64.
    HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64);

    // Set up a simulated exception return.
    SPSR_EL2.write(
        SPSR_EL2::D::Masked
            + SPSR_EL2::A::Masked
            + SPSR_EL2::I::Masked
            + SPSR_EL2::F::Masked
            + SPSR_EL2::M::EL1h,
    );
}

Disclaimer

Descriptive comments in the source files are taken from the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

License

Licensed under either of

• Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
• MIT License (LICENSE-MIT or http://opensource.org/licenses/MIT)

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the Cortex-A team, promises to intervene to uphold that code of conduct.

Changelog

[v10.0.0] - 2024-10-26

Breaking

Major version bump due to tock-registers dependency - updated to 0.9 (#26)

Added

• Add automatic release pipeline (#30)

• Re-export tock-registers::interfaces::ReadWriteable (#23)

• Add register CNTHP_CTL_EL2 (#24) - "Control register for the EL2 physical timer"

• Add EL3h and EL3t fields to register SPSR_EL3 (#28)

• Add registers CNTPOFF_EL2, CPTR_EL2, HPFAR_EL2, ICC_CTLR_EL1, ICC_SRE_EL2, ICH_AP0R_EL2, ICH_AP1R_EL2, ICH_HCR_EL2, ICH_LR_EL2, ICH_MISR_EL2, ICH_VMCR_EL2, ICH_VTR_EL2, ID_AA64AFR0_EL1, ID_AA64AFR1_EL1, ID_AA64DFR0_EL1, ID_AA64DFR1_EL1, ID_AA64ISAR1_EL1, ID_AA64PFR0_EL1, ID_AA64PFR1_EL1 (#27)

• Add fields TERR, TLOR, TSW, TACR, TIDCP, TID3, BSU, FB to register HCR_EL2 (#27)

• Add fields to register ICH_LR0_EL2 (#27)

• Add field EOS to register SCTLR_EL2 (#27)

• Add fields NSA and SL0 to register VTCR_EL2 (#27)

Fixed

• Fix writing ESL_EL1 with register bitfield instead of u64 (#27)