ipxact2systemverilog
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description
Readme
This software takes an IP-XACT description of register banks, and generates synthesizable VHDL and SystemVerilog packages and ReStructuredText documents. It ONLY considers register bank descriptions. The software does not generate OVM or UVM test bench packages. In the example/tb directory there is an example of how to use the generated packages.
pip install ipxact2systemverilog
ipxact2systemverilog --srcFile FILE --destDir DIR
ipxact2rst --srcFile FILE --destDir DIR
ipxact2md --srcFile FILE --destDir DIR
ipxact2vhdl --srcFile FILE --destDir DIR
ipxact2c --srcFile FILE --destDir DIR
See https://github.com/oddball/ipxact2systemverilog
make
If Modelsim is installed: :
make compile
make sim
You can use http://pandoc.org/demos.html to convert to almost any fileformat.
To validate your xml :
xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/test.xml
pip install docutils lxml mdutils
These are not needed for ipxact2systemverilog, but used for generating some of the files in example/output
brew install pandoc
# needed for sphinx
brew install texlive
sudo tlmgr install latexmk
rm -rf dist
pip3 install -e .
python3 setup.py sdist
twine upload dist/*
FAQs
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description
We found that ipxact2systemverilog demonstrated a healthy version release cadence and project activity because the last version was released less than a year ago. It has 1 open source maintainer collaborating on the project.
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