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dw-cache - npm Package Compare versions

Comparing version 0.0.108 to 0.0.109

1

index.d.ts
export * from 'spica/cache';
export * from 'spica/tlru';

1

index.ts
export * from 'spica/cache';
export * from 'spica/tlru';

14

package.json
{
"name": "dw-cache",
"version": "0.0.108",
"version": "0.0.109",
"description": "The highest performance constant complexity cache algorithm.",

@@ -33,3 +33,3 @@ "private": false,

"dependencies": {
"spica": "0.0.768"
"spica": "0.0.777"
},

@@ -40,3 +40,3 @@ "devDependencies": {

"@types/power-assert": "1.5.12",
"@typescript-eslint/parser": "^6.17.0",
"@typescript-eslint/parser": "^6.19.1",
"babel-loader": "^9.1.3",

@@ -55,8 +55,8 @@ "babel-plugin-unassert": "^3.2.0",

"karma-power-assert": "^1.0.0",
"lru-cache": "^10.1.0",
"lru-cache": "^10.2.0",
"mocha": "^10.2.0",
"npm-check-updates": "^16.14.12",
"npm-check-updates": "^16.14.14",
"ts-loader": "^9.5.1",
"typescript": "5.2.2",
"webpack": "^5.89.0",
"typescript": "5.3.3",
"webpack": "^5.90.0",
"webpack-cli": "^5.1.4",

@@ -63,0 +63,0 @@ "webpack-merge": "^5.10.0",

291

README.md

@@ -15,2 +15,4 @@ # Dual Window Cache

TLRU and TRC are abbreviations for TrueLRU (spica/tlru).
### Mathematical efficiency

@@ -25,2 +27,3 @@

|LRU |Evict|Constant|Constant| 1x |1 list |
|TLRU |Evict|Constant|Constant| 1x |1 list |
|DWC |Evict|Constant|Constant| 1x |2 lists|

@@ -46,2 +49,3 @@ |ARC |Evict|Constant|Linear | 2x |4 lists|

|LRU | 16 bytes| 1x| 32 bytes| 100.00%|
|TLRU | 16 bytes| 1x| 32 bytes| 100.00%|
|DWC | 17 bytes| 1x| 33 bytes| 96.96%|

@@ -61,2 +65,3 @@ |ARC | 17 bytes| 2x| 58 bytes| 55.17%|

|LRU | 16 bytes| 1x| 56 bytes| 100.00%|
|TLRU | 16 bytes| 1x| 56 bytes| 100.00%|
|DWC | 17 bytes| 1x| 57 bytes| 98.24%|

@@ -76,2 +81,3 @@ |ARC | 17 bytes| 2x| 88 bytes| 63.63%|

|LRU | 16 bytes| 1x| 544 bytes| 100.00%|
|TLRU | 16 bytes| 1x| 544 bytes| 100.00%|
|DWC | 17 bytes| 1x| 545 bytes| 99.81%|

@@ -87,2 +93,3 @@ |ARC | 17 bytes| 2x| 578 bytes| 94.11%|

LIRS's burst resistance means the resistance to continuous cache misses for the last LIR entry or the HIR entries.
TLRU's loop resistance is limited.

@@ -92,2 +99,3 @@ |Algorithm|Type |Scan|Loop|Burst|

|LRU |Evict| | | ✓ |
|TLRU |Evict| ✓ | ✓ | ✓ |
|DWC |Evict| ✓ | ✓ | ✓ |

@@ -144,2 +152,6 @@ |ARC |Evict| ✓ | | ✓ |

- Cache size 1,000 or more is recommended.
- For discontinuous workloads, TLRU is better.
- No tradeoffs other than hit ratio
- Other advanced cache algorithms have some tradeoffs such as spike latency by linear time complexity, delayed memory release by linear space complexity, or implementability.
- Other advanced cache algorithms cannot generally replace LRU due to these tradeoffs.

@@ -154,2 +166,10 @@ ## Tradeoffs

- **Scan access clears all entries.**
- TLRU
- Middle performance
- Lower hit ratio than DWC.
- Limited resistance
- Limited loop resistance.
- DWC
- Not the highest hit ratio
- Statistical accuracy dependent
- ARC

@@ -163,5 +183,2 @@ - Middle performance

- No loop resistance.
- DWC
- Not the highest hit ratio
- Statistical accuracy dependent
- LIRS

@@ -270,2 +287,7 @@ - Extremely inefficient

{
label: 'TrueLRU',
data: [7.94, 21.70, 33.46, 39.28, 46.10, 53.28, 60.42, 68.74],
borderColor: Utils.color(1),
},
{
label: 'LIRS',

@@ -289,5 +311,5 @@ data: [12.98, 26.85, 38.02, 38.14, 38.18, 47.25, 59.89, 71.74],

![image](https://github.com/falsandtru/dw-cache/assets/3143368/57c88cdd-9c1e-498f-a656-f56f20bab079)
![image](https://github.com/falsandtru/dw-cache/assets/3143368/744260e0-4fb7-4a89-bd30-731c9c3d9399)
W-TinyLFU, (TinyLFU) > DWC > (LIRS) > ARC > LRU
W-TinyLFU, (TinyLFU) > DWC > (LIRS) > TLRU > ARC > LRU

@@ -299,2 +321,3 @@ - DWC is an approximation of W-TinyLFU.

LRU hit ratio 3.08%
TRC hit ratio 7.94%
DWC hit ratio 14.73%

@@ -306,2 +329,3 @@ DWC - LRU hit ratio delta 11.65%

LRU hit ratio 10.74%
TRC hit ratio 21.70%
DWC hit ratio 27.94%

@@ -313,2 +337,3 @@ DWC - LRU hit ratio delta 17.20%

LRU hit ratio 18.59%
TRC hit ratio 33.46%
DWC hit ratio 39.46%

@@ -320,2 +345,3 @@ DWC - LRU hit ratio delta 20.87%

LRU hit ratio 20.24%
TRC hit ratio 39.28%
DWC hit ratio 44.20%

@@ -327,2 +353,3 @@ DWC - LRU hit ratio delta 23.96%

LRU hit ratio 21.03%
TRC hit ratio 46.10%
DWC hit ratio 50.19%

@@ -334,2 +361,3 @@ DWC - LRU hit ratio delta 29.16%

LRU hit ratio 33.95%
TRC hit ratio 53.28%
DWC hit ratio 56.83%

@@ -341,2 +369,3 @@ DWC - LRU hit ratio delta 22.88%

LRU hit ratio 38.89%
TRC hit ratio 60.42%
DWC hit ratio 62.55%

@@ -348,2 +377,3 @@ DWC - LRU hit ratio delta 23.65%

LRU hit ratio 43.03%
TRC hit ratio 68.74%
DWC hit ratio 70.03%

@@ -380,2 +410,7 @@ DWC - LRU hit ratio delta 26.99%

{
label: 'TrueLRU',
data: [3.96, 12.98, 21.55, 30.31, 38.81, 47.22, 55.58, 64.00],
borderColor: Utils.color(1),
},
{
label: 'LIRS',

@@ -399,5 +434,5 @@ data: [12.4, 15.55, 25.08, 34.69, 44.27, 53.15, 60.99, 67.64],

![image](https://github.com/falsandtru/dw-cache/assets/3143368/bb3f3eac-3193-4f22-90d8-2cc819e073fb)
![image](https://github.com/falsandtru/dw-cache/assets/3143368/72bf6cdc-6351-4c3c-b019-d6f55845f4b9)
W-TinyLFU, (TinyLFU) > (LIRS) > DWC > ARC > LRU
W-TinyLFU, (TinyLFU) > (LIRS) > DWC > TLRU, ARC > LRU

@@ -409,2 +444,3 @@ - DWC is an approximation of ARC.

LRU hit ratio 2.32%
TRC hit ratio 3.96%
DWC hit ratio 10.14%

@@ -416,2 +452,3 @@ DWC - LRU hit ratio delta 7.81%

LRU hit ratio 4.63%
TRC hit ratio 12.98%
DWC hit ratio 20.25%

@@ -423,2 +460,3 @@ DWC - LRU hit ratio delta 15.61%

LRU hit ratio 7.58%
TRC hit ratio 21.55%
DWC hit ratio 27.39%

@@ -430,2 +468,3 @@ DWC - LRU hit ratio delta 19.80%

LRU hit ratio 12.03%
TRC hit ratio 30.31%
DWC hit ratio 32.69%

@@ -437,2 +476,3 @@ DWC - LRU hit ratio delta 20.65%

LRU hit ratio 22.76%
TRC hit ratio 38.81%
DWC hit ratio 38.12%

@@ -444,2 +484,3 @@ DWC - LRU hit ratio delta 15.35%

LRU hit ratio 34.63%
TRC hit ratio 47.22%
DWC hit ratio 46.82%

@@ -451,2 +492,3 @@ DWC - LRU hit ratio delta 12.19%

LRU hit ratio 46.04%
TRC hit ratio 55.58%
DWC hit ratio 55.71%

@@ -458,2 +500,3 @@ DWC - LRU hit ratio delta 9.66%

LRU hit ratio 56.59%
TRC hit ratio 64.00%
DWC hit ratio 64.03%

@@ -490,2 +533,7 @@ DWC - LRU hit ratio delta 7.43%

{
label: 'TrueLRU',
data: [16.92, 28.52, 33.50, 37.01, 39.18, 41.19, 42.65, 43.95],
borderColor: Utils.color(1),
},
{
label: 'LIRS',

@@ -509,5 +557,5 @@ data: [18.27, 26.87, 31.71, 34.82, 37.24, 39.2, 40.79, 42.52],

![image](https://github.com/falsandtru/dw-cache/assets/3143368/1861b8c7-1ca4-492e-bf72-0019a8a180c3)
![image](https://github.com/falsandtru/dw-cache/assets/3143368/aa5336fc-e9f2-4d6a-97bc-59a0aa8e2f20)
ARC > DWC > W-TinyLFU > (LIRS) > LRU > (TinyLFU)
ARC > DWC > TLRU > W-TinyLFU > (LIRS) > LRU > (TinyLFU)

@@ -519,2 +567,3 @@ - DWC is an approximation of ARC.

LRU hit ratio 16.47%
TRC hit ratio 16.92%
DWC hit ratio 19.59%

@@ -526,2 +575,3 @@ DWC - LRU hit ratio delta 3.11%

LRU hit ratio 23.44%
TRC hit ratio 28.52%
DWC hit ratio 29.12%

@@ -533,2 +583,3 @@ DWC - LRU hit ratio delta 5.68%

LRU hit ratio 28.28%
TRC hit ratio 33.50%
DWC hit ratio 34.90%

@@ -540,2 +591,3 @@ DWC - LRU hit ratio delta 6.62%

LRU hit ratio 32.83%
TRC hit ratio 37.01%
DWC hit ratio 37.93%

@@ -547,2 +599,3 @@ DWC - LRU hit ratio delta 5.10%

LRU hit ratio 36.20%
TRC hit ratio 39.18%
DWC hit ratio 39.96%

@@ -554,2 +607,3 @@ DWC - LRU hit ratio delta 3.75%

LRU hit ratio 38.69%
TRC hit ratio 41.19%
DWC hit ratio 41.79%

@@ -561,2 +615,3 @@ DWC - LRU hit ratio delta 3.09%

LRU hit ratio 40.78%
TRC hit ratio 42.65%
DWC hit ratio 43.43%

@@ -568,2 +623,3 @@ DWC - LRU hit ratio delta 2.64%

LRU hit ratio 42.46%
TRC hit ratio 43.95%
DWC hit ratio 44.70%

@@ -600,2 +656,7 @@ DWC - LRU hit ratio delta 2.23%

{
label: 'TrueLRU',
data: [10.48, 23.88, 36.31, 46.82, 52.04, 53.00, 55.88, 57.96],
borderColor: Utils.color(1),
},
{
label: 'LIRS',

@@ -619,5 +680,5 @@ data: [15.91, 33.6, 43.61, 50.56, 51.85, 53.55, 55.58, 57.96],

![image](https://github.com/falsandtru/dw-cache/assets/3143368/83ecb920-246f-41d7-90f5-93820aba2ce6)
![image](https://github.com/falsandtru/dw-cache/assets/3143368/d9e57f61-7cc8-4e37-b57a-46d360b8d476)
W-TinyLFU, (TinyLFU), (LIRS) > DWC >> ARC > LRU
W-TinyLFU, (TinyLFU), (LIRS) > DWC > TLRU >> ARC > LRU

@@ -629,2 +690,3 @@ - DWC is an approximation of W-TinyLFU.

LRU hit ratio 0.93%
TRC hit ratio 10.48%
DWC hit ratio 15.44%

@@ -636,2 +698,3 @@ DWC - LRU hit ratio delta 14.51%

LRU hit ratio 0.96%
TRC hit ratio 23.88%
DWC hit ratio 31.53%

@@ -643,2 +706,3 @@ DWC - LRU hit ratio delta 30.56%

LRU hit ratio 1.16%
TRC hit ratio 36.31%
DWC hit ratio 41.55%

@@ -650,2 +714,3 @@ DWC - LRU hit ratio delta 40.39%

LRU hit ratio 11.22%
TRC hit ratio 46.82%
DWC hit ratio 49.30%

@@ -657,2 +722,3 @@ DWC - LRU hit ratio delta 38.08%

LRU hit ratio 21.25%
TRC hit ratio 52.04%
DWC hit ratio 52.42%

@@ -664,2 +730,3 @@ DWC - LRU hit ratio delta 31.16%

LRU hit ratio 36.56%
TRC hit ratio 53.00%
DWC hit ratio 53.49%

@@ -671,2 +738,3 @@ DWC - LRU hit ratio delta 16.92%

LRU hit ratio 45.04%
TRC hit ratio 55.88%
DWC hit ratio 55.60%

@@ -678,2 +746,3 @@ DWC - LRU hit ratio delta 10.55%

LRU hit ratio 57.41%
TRC hit ratio 57.96%
DWC hit ratio 57.96%

@@ -688,2 +757,3 @@ DWC - LRU hit ratio delta 0.54%

LRU hit ratio 0.00%
TRC hit ratio 0.00%
DWC hit ratio 8.12%

@@ -695,2 +765,3 @@ DWC - LRU hit ratio delta 8.12%

LRU hit ratio 0.00%
TRC hit ratio 0.00%
DWC hit ratio 21.33%

@@ -702,2 +773,3 @@ DWC - LRU hit ratio delta 21.33%

LRU hit ratio 0.00%
TRC hit ratio 0.00%
DWC hit ratio 44.42%

@@ -709,2 +781,3 @@ DWC - LRU hit ratio delta 44.42%

LRU hit ratio 0.00%
TRC hit ratio 0.00%
DWC hit ratio 67.62%

@@ -716,2 +789,3 @@ DWC - LRU hit ratio delta 67.62%

LRU hit ratio 0.00%
TRC hit ratio 0.00%
DWC hit ratio 96.77%

@@ -723,2 +797,3 @@ DWC - LRU hit ratio delta 96.77%

LRU hit ratio 99.80%
TRC hit ratio 99.80%
DWC hit ratio 99.80%

@@ -730,2 +805,3 @@ DWC - LRU hit ratio delta 0.00%

LRU hit ratio 2.95%
TRC hit ratio 6.97%
DWC hit ratio 10.37%

@@ -737,2 +813,3 @@ DWC - LRU hit ratio delta 7.42%

LRU hit ratio 6.08%
TRC hit ratio 17.18%
DWC hit ratio 18.37%

@@ -744,2 +821,3 @@ DWC - LRU hit ratio delta 12.28%

LRU hit ratio 9.63%
TRC hit ratio 26.32%
DWC hit ratio 21.94%

@@ -751,2 +829,3 @@ DWC - LRU hit ratio delta 12.31%

LRU hit ratio 21.59%
TRC hit ratio 35.30%
DWC hit ratio 27.22%

@@ -758,2 +837,3 @@ DWC - LRU hit ratio delta 5.62%

LRU hit ratio 33.91%
TRC hit ratio 43.80%
DWC hit ratio 37.77%

@@ -765,2 +845,3 @@ DWC - LRU hit ratio delta 3.86%

LRU hit ratio 45.74%
TRC hit ratio 51.37%
DWC hit ratio 48.43%

@@ -772,2 +853,3 @@ DWC - LRU hit ratio delta 2.69%

LRU hit ratio 54.89%
TRC hit ratio 57.48%
DWC hit ratio 56.74%

@@ -779,2 +861,3 @@ DWC - LRU hit ratio delta 1.85%

LRU hit ratio 61.40%
TRC hit ratio 62.34%
DWC hit ratio 62.11%

@@ -786,2 +869,3 @@ DWC - LRU hit ratio delta 0.71%

LRU hit ratio 27.74%
TRC hit ratio 27.85%
DWC hit ratio 25.12%

@@ -793,2 +877,3 @@ DWC - LRU hit ratio delta -2.61%

LRU hit ratio 30.55%
TRC hit ratio 31.72%
DWC hit ratio 30.20%

@@ -800,2 +885,3 @@ DWC - LRU hit ratio delta -0.35%

LRU hit ratio 32.18%
TRC hit ratio 34.25%
DWC hit ratio 33.85%

@@ -807,2 +893,3 @@ DWC - LRU hit ratio delta 1.67%

LRU hit ratio 33.27%
TRC hit ratio 35.73%
DWC hit ratio 35.64%

@@ -814,2 +901,3 @@ DWC - LRU hit ratio delta 2.36%

LRU hit ratio 34.19%
TRC hit ratio 36.75%
DWC hit ratio 36.73%

@@ -821,2 +909,3 @@ DWC - LRU hit ratio delta 2.54%

LRU hit ratio 34.97%
TRC hit ratio 37.69%
DWC hit ratio 37.61%

@@ -828,2 +917,3 @@ DWC - LRU hit ratio delta 2.64%

LRU hit ratio 35.62%
TRC hit ratio 38.31%
DWC hit ratio 38.17%

@@ -835,2 +925,3 @@ DWC - LRU hit ratio delta 2.55%

LRU hit ratio 36.17%
TRC hit ratio 38.83%
DWC hit ratio 38.80%

@@ -856,114 +947,160 @@ DWC - LRU hit ratio delta 2.63%

Clock: spica/clock<br>
ISCCache: [lru-cache](https://www.npmjs.com/package/lru-cache)<br>
LRUCache: spica/lru<br>
DW-Cache: spica/cache<br>
ISC: [lru-cache](https://www.npmjs.com/package/lru-cache)<br>
LRU: spica/lru<br>
TRC-C: spica/tlru (spica/trul.clock)<br>
TRC-L: spica/trul.lru<br>
DWC: spica/cache<br>
```
'Clock new x 1,650,836 ops/sec ±1.94% (94 runs sampled)'
'Clock new x 1,552,561 ops/sec ±1.66% (113 runs sampled)'
'ISCCache new x 18,042 ops/sec ±0.66% (105 runs sampled)'
'ISC new x 17,669 ops/sec ±0.83% (122 runs sampled)'
'LRUCache new x 30,098,951 ops/sec ±0.23% (106 runs sampled)'
'LRU new x 26,469,709 ops/sec ±0.93% (121 runs sampled)'
'DW-Cache new x 7,021,323 ops/sec ±0.30% (105 runs sampled)'
'TRC-C new x 24,865,728 ops/sec ±0.89% (120 runs sampled)'
'Clock simulation 100 10% x 9,762,593 ops/sec ±0.36% (107 runs sampled)'
'TRC-L new x 25,006,319 ops/sec ±0.91% (122 runs sampled)'
'ISCCache simulation 100 10% x 8,761,469 ops/sec ±0.38% (107 runs sampled)'
'DWC new x 6,775,282 ops/sec ±0.94% (121 runs sampled)'
'LRUCache simulation 100 10% x 10,769,407 ops/sec ±0.28% (107 runs sampled)'
'Clock simulation 100 10% x 9,363,738 ops/sec ±0.61% (121 runs sampled)'
'DW-Cache simulation 100 10% x 7,242,192 ops/sec ±0.50% (105 runs sampled)'
'ISC simulation 100 10% x 9,008,687 ops/sec ±0.80% (121 runs sampled)'
'Clock simulation 1,000 10% x 9,601,967 ops/sec ±0.48% (107 runs sampled)'
'LRU simulation 100 10% x 10,725,903 ops/sec ±0.56% (121 runs sampled)'
'ISCCache simulation 1,000 10% x 7,986,140 ops/sec ±0.58% (106 runs sampled)'
'TRC-C simulation 100 10% x 10,571,693 ops/sec ±0.64% (122 runs sampled)'
'LRUCache simulation 1,000 10% x 9,735,550 ops/sec ±0.41% (106 runs sampled)'
'TRC-L simulation 100 10% x 8,459,734 ops/sec ±0.78% (122 runs sampled)'
'DW-Cache simulation 1,000 10% x 6,592,345 ops/sec ±0.37% (107 runs sampled)'
'DWC simulation 100 10% x 6,584,195 ops/sec ±0.42% (123 runs sampled)'
'Clock simulation 10,000 10% x 9,344,809 ops/sec ±0.40% (105 runs sampled)'
'Clock simulation 1,000 10% x 9,384,521 ops/sec ±0.60% (122 runs sampled)'
'ISCCache simulation 10,000 10% x 7,193,304 ops/sec ±0.83% (106 runs sampled)'
'ISC simulation 1,000 10% x 8,268,271 ops/sec ±0.96% (121 runs sampled)'
'LRUCache simulation 10,000 10% x 8,881,517 ops/sec ±0.41% (104 runs sampled)'
'LRU simulation 1,000 10% x 9,449,176 ops/sec ±0.79% (122 runs sampled)'
'DW-Cache simulation 10,000 10% x 6,020,040 ops/sec ±0.50% (106 runs sampled)'
'TRC-C simulation 1,000 10% x 9,205,839 ops/sec ±0.45% (121 runs sampled)'
'Clock simulation 100,000 10% x 5,948,133 ops/sec ±1.22% (101 runs sampled)'
'TRC-L simulation 1,000 10% x 8,005,839 ops/sec ±0.95% (122 runs sampled)'
'ISCCache simulation 100,000 10% x 3,654,505 ops/sec ±1.47% (101 runs sampled)'
'DWC simulation 1,000 10% x 7,532,780 ops/sec ±0.59% (122 runs sampled)'
'LRUCache simulation 100,000 10% x 5,615,930 ops/sec ±1.35% (100 runs sampled)'
'Clock simulation 10,000 10% x 9,359,627 ops/sec ±0.79% (122 runs sampled)'
'DW-Cache simulation 100,000 10% x 4,255,377 ops/sec ±1.79% (97 runs sampled)'
'ISC simulation 10,000 10% x 6,781,153 ops/sec ±0.72% (121 runs sampled)'
'Clock simulation 1,000,000 10% x 2,605,647 ops/sec ±3.98% (93 runs sampled)'
'LRU simulation 10,000 10% x 8,730,973 ops/sec ±0.72% (120 runs sampled)'
'ISCCache simulation 1,000,000 10% x 1,453,643 ops/sec ±2.92% (95 runs sampled)'
'TRC-C simulation 10,000 10% x 8,021,631 ops/sec ±2.00% (119 runs sampled)'
'LRUCache simulation 1,000,000 10% x 2,081,983 ops/sec ±4.23% (88 runs sampled)'
'TRC-L simulation 10,000 10% x 6,130,857 ops/sec ±2.73% (116 runs sampled)'
'DW-Cache simulation 1,000,000 10% x 2,598,274 ops/sec ±4.42% (89 runs sampled)'
'DWC simulation 10,000 10% x 5,836,941 ops/sec ±1.04% (122 runs sampled)'
'Clock simulation 100 90% x 25,014,146 ops/sec ±0.33% (107 runs sampled)'
'Clock simulation 100,000 10% x 5,590,625 ops/sec ±1.73% (115 runs sampled)'
'ISCCache simulation 100 90% x 22,495,828 ops/sec ±0.74% (105 runs sampled)'
'ISC simulation 100,000 10% x 3,278,209 ops/sec ±1.70% (111 runs sampled)'
'LRUCache simulation 100 90% x 20,969,655 ops/sec ±0.84% (107 runs sampled)'
'LRU simulation 100,000 10% x 4,765,807 ops/sec ±2.79% (111 runs sampled)'
'DW-Cache simulation 100 90% x 9,730,398 ops/sec ±0.32% (107 runs sampled)'
'TRC-C simulation 100,000 10% x 4,685,016 ops/sec ±2.90% (105 runs sampled)'
'Clock simulation 1,000 90% x 23,025,311 ops/sec ±0.51% (107 runs sampled)'
'TRC-L simulation 100,000 10% x 4,150,880 ops/sec ±2.95% (111 runs sampled)'
'ISCCache simulation 1,000 90% x 19,347,819 ops/sec ±0.34% (107 runs sampled)'
'DWC simulation 100,000 10% x 3,822,807 ops/sec ±2.51% (108 runs sampled)'
'LRUCache simulation 1,000 90% x 18,240,448 ops/sec ±0.28% (107 runs sampled)'
'Clock simulation 1,000,000 10% x 2,280,505 ops/sec ±4.09% (97 runs sampled)'
'DW-Cache simulation 1,000 90% x 11,382,934 ops/sec ±0.19% (108 runs sampled)'
'ISC simulation 1,000,000 10% x 1,241,084 ops/sec ±4.17% (101 runs sampled)'
'Clock simulation 10,000 90% x 20,506,917 ops/sec ±0.25% (105 runs sampled)'
'LRU simulation 1,000,000 10% x 1,742,529 ops/sec ±3.63% (89 runs sampled)'
'ISCCache simulation 10,000 90% x 15,441,103 ops/sec ±1.24% (105 runs sampled)'
'TRC-C simulation 1,000,000 10% x 1,973,322 ops/sec ±5.40% (88 runs sampled)'
'LRUCache simulation 10,000 90% x 13,104,661 ops/sec ±0.61% (105 runs sampled)'
'TRC-L simulation 1,000,000 10% x 1,644,990 ops/sec ±4.36% (97 runs sampled)'
'DW-Cache simulation 10,000 90% x 8,747,757 ops/sec ±0.92% (107 runs sampled)'
'DWC simulation 1,000,000 10% x 1,951,708 ops/sec ±3.92% (98 runs sampled)'
'Clock simulation 100,000 90% x 12,049,875 ops/sec ±1.49% (100 runs sampled)'
'Clock simulation 100 90% x 21,254,002 ops/sec ±0.68% (123 runs sampled)'
'ISCCache simulation 100,000 90% x 8,173,371 ops/sec ±1.17% (102 runs sampled)'
'ISC simulation 100 90% x 19,742,448 ops/sec ±0.62% (122 runs sampled)'
'LRUCache simulation 100,000 90% x 8,188,424 ops/sec ±2.08% (100 runs sampled)'
'LRU simulation 100 90% x 18,749,189 ops/sec ±0.68% (122 runs sampled)'
'DW-Cache simulation 100,000 90% x 5,973,422 ops/sec ±2.65% (100 runs sampled)'
'TRC-C simulation 100 90% x 16,785,649 ops/sec ±0.63% (122 runs sampled)'
'Clock simulation 1,000,000 90% x 5,578,321 ops/sec ±4.20% (92 runs sampled)'
'TRC-L simulation 100 90% x 16,148,417 ops/sec ±0.80% (122 runs sampled)'
'ISCCache simulation 1,000,000 90% x 2,963,294 ops/sec ±2.91% (95 runs sampled)'
'DWC simulation 100 90% x 10,688,142 ops/sec ±0.60% (121 runs sampled)'
'LRUCache simulation 1,000,000 90% x 2,235,658 ops/sec ±2.83% (95 runs sampled)'
'Clock simulation 1,000 90% x 19,744,639 ops/sec ±0.85% (122 runs sampled)'
'DW-Cache simulation 1,000,000 90% x 1,931,442 ops/sec ±2.32% (98 runs sampled)'
'ISC simulation 1,000 90% x 17,049,505 ops/sec ±0.90% (121 runs sampled)'
'ISCCache simulation 100 90% expire x 4,172,541 ops/sec ±5.34% (94 runs sampled)'
'LRU simulation 1,000 90% x 16,579,637 ops/sec ±0.58% (122 runs sampled)'
'DW-Cache simulation 100 90% expire x 8,241,722 ops/sec ±0.42% (107 runs sampled)'
'TRC-C simulation 1,000 90% x 15,110,520 ops/sec ±0.63% (121 runs sampled)'
'ISCCache simulation 1,000 90% expire x 4,169,949 ops/sec ±3.98% (97 runs sampled)'
'TRC-L simulation 1,000 90% x 14,668,067 ops/sec ±0.55% (122 runs sampled)'
'DW-Cache simulation 1,000 90% expire x 8,218,212 ops/sec ±0.30% (107 runs sampled)'
'DWC simulation 1,000 90% x 8,654,990 ops/sec ±0.44% (123 runs sampled)'
'ISCCache simulation 10,000 90% expire x 3,539,574 ops/sec ±4.02% (98 runs sampled)'
'Clock simulation 10,000 90% x 17,330,494 ops/sec ±1.05% (121 runs sampled)'
'DW-Cache simulation 10,000 90% expire x 6,338,384 ops/sec ±1.07% (105 runs sampled)'
'ISC simulation 10,000 90% x 13,822,754 ops/sec ±0.54% (122 runs sampled)'
'ISCCache simulation 100,000 90% expire x 2,429,074 ops/sec ±4.48% (94 runs sampled)'
'LRU simulation 10,000 90% x 11,492,835 ops/sec ±1.18% (120 runs sampled)'
'DW-Cache simulation 100,000 90% expire x 1,977,169 ops/sec ±2.71% (86 runs sampled)'
'TRC-C simulation 10,000 90% x 10,603,672 ops/sec ±1.00% (121 runs sampled)'
'ISCCache simulation 1,000,000 90% expire x 448,719 ops/sec ±5.09% (82 runs sampled)'
'TRC-L simulation 10,000 90% x 9,814,431 ops/sec ±1.61% (119 runs sampled)'
'DW-Cache simulation 1,000,000 90% expire x 629,254 ops/sec ±3.81% (98 runs sampled)'
'DWC simulation 10,000 90% x 7,915,551 ops/sec ±0.91% (121 runs sampled)'
'Clock simulation 100,000 90% x 10,156,702 ops/sec ±1.60% (113 runs sampled)'
'ISC simulation 100,000 90% x 7,467,007 ops/sec ±1.15% (117 runs sampled)'
'LRU simulation 100,000 90% x 7,179,007 ops/sec ±2.16% (117 runs sampled)'
'TRC-C simulation 100,000 90% x 6,660,546 ops/sec ±2.31% (112 runs sampled)'
'TRC-L simulation 100,000 90% x 6,263,904 ops/sec ±2.89% (110 runs sampled)'
'DWC simulation 100,000 90% x 5,045,747 ops/sec ±4.65% (111 runs sampled)'
'Clock simulation 1,000,000 90% x 3,587,431 ops/sec ±4.83% (96 runs sampled)'
'ISC simulation 1,000,000 90% x 2,312,996 ops/sec ±3.32% (104 runs sampled)'
'LRU simulation 1,000,000 90% x 1,770,884 ops/sec ±2.79% (102 runs sampled)'
'TRC-C simulation 1,000,000 90% x 1,803,313 ops/sec ±3.00% (105 runs sampled)'
'TRC-L simulation 1,000,000 90% x 1,649,346 ops/sec ±1.57% (113 runs sampled)'
'DWC simulation 1,000,000 90% x 1,589,534 ops/sec ±1.67% (115 runs sampled)'
'ISC simulation 100 90% expire x 4,261,673 ops/sec ±4.13% (112 runs sampled)'
'DWC simulation 100 90% expire x 7,782,281 ops/sec ±0.41% (123 runs sampled)'
'ISC simulation 1,000 90% expire x 3,984,608 ops/sec ±4.70% (109 runs sampled)'
'DWC simulation 1,000 90% expire x 7,160,830 ops/sec ±0.87% (121 runs sampled)'
'ISC simulation 10,000 90% expire x 3,594,196 ops/sec ±2.68% (115 runs sampled)'
'DWC simulation 10,000 90% expire x 5,985,963 ops/sec ±1.45% (120 runs sampled)'
'ISC simulation 100,000 90% expire x 2,442,721 ops/sec ±3.29% (104 runs sampled)'
'DWC simulation 100,000 90% expire x 2,143,528 ops/sec ±4.06% (108 runs sampled)'
'ISC simulation 1,000,000 90% expire x 476,958 ops/sec ±5.88% (91 runs sampled)'
'DWC simulation 1,000,000 90% expire x 582,347 ops/sec ±4.32% (106 runs sampled)'
```

@@ -1010,2 +1147,4 @@

constructor(opts: Cache.Options<K, V>);
readonly length: number;
readonly size: number;
add(key: K, value: V, opts?: { size?: number; age?: number; }): boolean;

@@ -1022,6 +1161,22 @@ add(this: Cache<K, undefined>, key: K, value?: V, opts?: { size?: number; age?: number; }): boolean;

resize(capacity: number, resource?: number): void;
[Symbol.iterator](): Iterator<[K, V], undefined, undefined>;
}
export class TLRU<K, V> {
constructor(
capacity: number,
step: number = 1,
window: number = 100,
retrial: boolean = true,
);
readonly length: number;
readonly size: number;
add(key: K, value: V): boolean;
set(key: K, value: V): this;
get(key: K): V | undefined;
has(key: K): boolean;
delete(key: K): boolean;
clear(): void;
[Symbol.iterator](): Iterator<[K, V], undefined, undefined>;
}
```

1

test/integration/index.test.ts
import 'spica/cache.test';
import 'spica/tlru.clock.test';

8

test/interface/index.test.ts

@@ -1,2 +0,2 @@

import { Cache } from '../../index';
import { Cache, TLRU } from '../../index';

@@ -17,2 +17,8 @@ describe('Interface: Package', function () {

describe('TLRU', function () {
it('TLRU', function () {
assert(typeof TLRU === 'function');
});
});
});
dist/index.js

Sorry, the diff of this file is too big to display

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