Comparing version 0.0.24 to 0.0.25
@@ -1,2 +0,2 @@ | ||
/*! dw-cache v0.0.24 https://github.com/falsandtru/dw-cache | (c) 2021, falsandtru | (Apache-2.0 AND MPL-2.0) License */ | ||
/*! dw-cache v0.0.25 https://github.com/falsandtru/dw-cache | (c) 2021, falsandtru | (Apache-2.0 AND MPL-2.0) License */ | ||
require = function () { | ||
@@ -419,2 +419,6 @@ function r(e, n, t) { | ||
var _a, _b, _c; | ||
if (skip) { | ||
skip.value.clock = this.clock; | ||
skip.value.expiry = global_1.Infinity; | ||
} | ||
let size = (_a = skip === null || skip === void 0 ? void 0 : skip.value.size) !== null && _a !== void 0 ? _a : 0; | ||
@@ -430,4 +434,4 @@ if (margin - size <= 0) | ||
case LRU.length === 0: | ||
case LRU.length === 1 && LRU.last === skip: | ||
target = LFU.last; | ||
target = target !== skip ? target : target.prev; | ||
break; | ||
@@ -439,9 +443,8 @@ case lastIndex && lastIndex.clock < this.clock - this.life: | ||
case LFU.length > this.capacity * this.ratio / 100: | ||
const lastLFU = LFU.last; | ||
LRU.unshiftNode(lastLFU); | ||
lastLFU.value.overflow = OVF.unshift(lastLFU.value); | ||
target = LFU.last; | ||
LRU.unshiftNode(target); | ||
target.value.overflow = OVF.unshift(target.value); | ||
default: | ||
const lastLRU = LRU.last; | ||
target = lastLRU === skip ? lastLRU.prev : lastLRU; | ||
break; | ||
target = LRU.last; | ||
target = target !== skip ? target : target.prev !== skip ? target.prev : LFU.last; | ||
} | ||
@@ -469,4 +472,2 @@ this.dispose(target, void 0, true); | ||
const index = node.value; | ||
index.clock = this.clock; | ||
index.expiry = global_1.Infinity; | ||
this.ensure(size, node); | ||
@@ -565,10 +566,14 @@ index.clock = ++this.clockR; | ||
return; | ||
const rateR = rate(window, LRU[0], LRU[0] + LFU[0], LRU[1], LRU[1] + LFU[1]) * (50 + ratio); | ||
const rateF = rate(window, LFU[0], LRU[0] + LFU[0], LFU[1], LRU[1] + LFU[1]) * (150 - ratio); | ||
if (ratio > 0 && rateR > rateF || ratio > 0 && rateF * 3 < rate(window, LFU[1], LRU[1] + LFU[1], LFU[0], LRU[0] + LFU[0]) * (150 - ratio)) { | ||
if (indexes.LRU.length >= capacity * (100 - ratio) / 100) { | ||
const lenR = indexes.LRU.length; | ||
const lenF = indexes.LFU.length; | ||
const lenV = indexes.OVF.length; | ||
const r = (lenF + lenV) * 1000 / (lenR + lenF) | 0; | ||
const rateR = rate(window, LRU[0], LRU[0] + LFU[0], LRU[1], LRU[1] + LFU[1]) * (1 + r); | ||
const rateF = rate(window, LFU[0], LRU[0] + LFU[0], LFU[1], LRU[1] + LFU[1]) * (1001 - r); | ||
if (ratio > 0 && rateR > rateF || ratio > 0 && rateF < rate(window, LFU[1], LRU[1] + LFU[1], LFU[0], LRU[0] + LFU[0]) * (1001 - r) * 0.95) { | ||
if (lenR >= capacity * (100 - ratio) / 100) { | ||
--this.ratio; | ||
} | ||
} else if (ratio < limit && rateF > rateR) { | ||
if (indexes.LFU.length >= capacity * ratio / 100) { | ||
if (lenF >= capacity * ratio / 100) { | ||
++this.ratio; | ||
@@ -575,0 +580,0 @@ } |
{ | ||
"name": "dw-cache", | ||
"version": "0.0.24", | ||
"version": "0.0.25", | ||
"description": "Dual window cache adaptively coordinates the ratio of LRU to LFU using the two sliding windows.", | ||
@@ -54,3 +54,3 @@ "private": false, | ||
"power-assert": "^1.6.1", | ||
"spica": "0.0.505", | ||
"spica": "0.0.506", | ||
"tsify": "^5.0.4", | ||
@@ -57,0 +57,0 @@ "typescript": "4.5.5", |
@@ -21,39 +21,39 @@ # Dual Window Cache | ||
'Cache even 100' | ||
'LRU hit rate', 10.13 | ||
'DWC hit rate', 10.13 | ||
'LRU hit rate', 9.87 | ||
'DWC hit rate', 9.84 | ||
'DWC ratio', 0, 0 | ||
'DWC / LRU hit rate ratio', '100%' | ||
'DWC / LRU hit rate ratio', '99%' | ||
'Cache uneven 100' | ||
'LRU hit rate', 18.44 | ||
'DWC hit rate', 36.94 | ||
'DWC ratio', 95, 94 | ||
'DWC / LRU hit rate ratio', '200%' | ||
'LRU hit rate', 19.14 | ||
'DWC hit rate', 36.52 | ||
'DWC ratio', 95, 93 | ||
'DWC / LRU hit rate ratio', '190%' | ||
'Cache uneven 100 transitive distribution' | ||
'LRU hit rate', 19.2 | ||
'DWC hit rate', 37.55 | ||
'LRU hit rate', 17.74 | ||
'DWC hit rate', 37.15 | ||
'DWC ratio', 95, 95 | ||
'DWC / LRU hit rate ratio', '195%' | ||
'DWC / LRU hit rate ratio', '209%' | ||
'Cache uneven 100 transitive bias' | ||
'LRU hit rate', 10.75 | ||
'DWC hit rate', 10.75 | ||
'DWC ratio', 0, 0 | ||
'LRU hit rate', 10.99 | ||
'DWC hit rate', 11.02 | ||
'DWC ratio', 0, 1 | ||
'DWC / LRU hit rate ratio', '100%' | ||
'Cache uneven 100 sequential' | ||
'LRU hit rate', 14.39 | ||
'DWC hit rate', 38.34 | ||
'LRU hit rate', 13.47 | ||
'DWC hit rate', 37.53 | ||
'DWC ratio', 95, 95 | ||
'DWC / LRU hit rate ratio', '266%' | ||
'DWC / LRU hit rate ratio', '278%' | ||
'Cache uneven 100 adversarial' | ||
'LRU hit rate', 41.58 | ||
'DWC hit rate', 49.58 | ||
'DWC ratio', 92, 91 | ||
'LRU hit rate', 41.78 | ||
'DWC hit rate', 49.77 | ||
'DWC ratio', 94, 93 | ||
'DWC / LRU hit rate ratio', '119%' | ||
``` | ||
https://github.com/falsandtru/spica/runs/4997367975 | ||
https://github.com/falsandtru/spica/runs/4998610954 | ||
@@ -65,24 +65,24 @@ ### Benchmark | ||
``` | ||
'LRUCache simulation 100 x 4,414,567 ops/sec ±0.55% (67 runs sampled)' | ||
'LRUCache simulation 100 x 4,248,360 ops/sec ±0.96% (64 runs sampled)' | ||
'DW-Cache simulation 100 x 4,079,753 ops/sec ±0.40% (66 runs sampled)' | ||
'DW-Cache simulation 100 x 3,814,501 ops/sec ±0.71% (63 runs sampled)' | ||
'LRUCache simulation 1,000 x 4,048,706 ops/sec ±0.37% (67 runs sampled)' | ||
'LRUCache simulation 1,000 x 3,160,547 ops/sec ±6.42% (51 runs sampled)' | ||
'DW-Cache simulation 1,000 x 3,723,917 ops/sec ±3.68% (61 runs sampled)' | ||
'DW-Cache simulation 1,000 x 3,945,506 ops/sec ±1.11% (61 runs sampled)' | ||
'LRUCache simulation 10,000 x 2,775,494 ops/sec ±3.10% (61 runs sampled)' | ||
'LRUCache simulation 10,000 x 2,485,636 ops/sec ±2.86% (57 runs sampled)' | ||
'DW-Cache simulation 10,000 x 2,937,801 ops/sec ±3.20% (61 runs sampled)' | ||
'DW-Cache simulation 10,000 x 2,585,085 ops/sec ±3.09% (61 runs sampled)' | ||
'LRUCache simulation 100,000 x 1,504,291 ops/sec ±2.48% (53 runs sampled)' | ||
'LRUCache simulation 100,000 x 1,334,175 ops/sec ±3.50% (56 runs sampled)' | ||
'DW-Cache simulation 100,000 x 1,569,898 ops/sec ±6.24% (56 runs sampled)' | ||
'DW-Cache simulation 100,000 x 1,317,095 ops/sec ±6.04% (54 runs sampled)' | ||
'LRUCache simulation 1,000,000 x 917,715 ops/sec ±5.59% (56 runs sampled)' | ||
'LRUCache simulation 1,000,000 x 837,846 ops/sec ±6.75% (55 runs sampled)' | ||
'DW-Cache simulation 1,000,000 x 811,086 ops/sec ±6.81% (56 runs sampled)' | ||
'DW-Cache simulation 1,000,000 x 726,036 ops/sec ±8.35% (56 runs sampled)' | ||
``` | ||
https://github.com/falsandtru/spica/runs/4997379775 | ||
https://github.com/falsandtru/spica/runs/4998624993 | ||
@@ -89,0 +89,0 @@ ## API |
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