duh

Design ∪ Hardware

DUH (pronounced [dûx]) is a suite of tools for packaging reusable hardware components and designs. DUH enables the generation of JSON5 duh-documents for describing these components, and also enables export from these documents to output deliverables.

Install

First ensure Node Package Manager (npm) is installed or get npm. Then install

npm i duh

And test installation with duh --help

Quick start

The following base set of DUH tools can be used to generate a duh-document for hardware components and designs:

• Run duh init to create a base duh-document.

• Run duh-import-verilog-ports to import a port list from Verilog RTL of the component -> import verilog

• Run duh-portinf to infer mappings of portgroups to standard bus definitions AXI, AHB, TileLink, etc. (From the duhportinf package.)

• Run duh-portbundler to group ports, which are unassigned to a bus mapping, into structured bundles. (From the duhportinf package.)

• Run duh validate to test whether a given document conforms to the duh-document standard.

The following base set of DUH tools can be used to generate outputs from a valid duh-document:

• Run duh-export-scala to generate scala black box wrappers for the component.

Preprocess verilog top-level module

To run a verilog preprocessor on the top-level module, use:

verilator -E -Irtl mytop.v > mytop.preproc.v

or

vppreproc -Irtl mytop.v > mytop.preproc.v

Further help

Further information:

• block-ark for a walk-through example using the DUH suite on a standalone module to produce a valid duh-document that fully describes the mapping of ports to known bus definitions.

• the duh-document standard.

• duhportinf for the port inference DUH package that contains usage details of the duh-portinf and duh-portbundler tools.

Other DUH packages:

• duh-scala -- Scala/Chisel export
• duh-ipxact -- IP-XACT import / export
• duhportinf -- Bus interfaces inference
• duh-bus -- DUH Bus Definitions
• duh-schema -- DUH document JSON schema
• duh-core -- DUH core library