aigverse: A Python Library for Logic Networks, Synthesis, and Optimization
[!Important]
This project is still in the early stages of development. The API is subject to change, and some features may not be
fully implemented. I appreciate your patience and understanding as work to improve the library continues.
aigverse
is a Python framework designed to bridge the gap between logic synthesis and AI/ML applications. It allows
you to represent and manipulate logic circuits efficiently, making it easier to integrate logic synthesis tasks into
machine learning pipelines. By leveraging the
powerful EPFL Logic Synthesis Libraries,
particularly mockturtle, aigverse
provides a high-level Python interface to
state-of-the-art algorithms for And-Inverter Graph (AIG) manipulation and logic synthesis, widely used in formal
verification, hardware design, and optimization tasks.
Features
- Efficient Logic Representation: Use And-Inverter Graphs (AIGs) to model and manipulate logic circuits in Python.
- File Format Support: Read and write AIGER, Verilog, Bench, PLA, ... files for interoperability with other logic
synthesis tools.
- C++ Backend: Leverage the performance of the EPFL Logic Synthesis Libraries for fast logic synthesis and
optimization.
- High-Level API: Simplify logic synthesis tasks with a Pythonic interface for AIG manipulation and optimization.
- Integration with Machine Learning: Convenient integration with popular data science libraries.
Motivation
As AI and machine learning (ML) increasingly impact hardware design automation, there's a growing need for tools that
integrate logic synthesis with ML workflows. aigverse
provides a Python-friendly interface for logic synthesis, making
it easier to develop applications that blend both AI/ML and traditional circuit synthesis techniques. With aigverse
,
you can parse, manipulate, and optimize logic circuits directly from Python. Eventually, we aim to provide seamless
integration with popular ML libraries, enabling the development of novel AI-driven synthesis and optimization tools.
Installation
aigverse
requires Python 3.8+ and is built using the EPFL Logic Synthesis Libraries
with pybind11. To install aigverse
:
pip install aigverse
Usage
Basic Example: Creating an AIG
In aigverse
, you can create a simple And-Inverter Graph (AIG) and manipulate it using various logic operations.
from aigverse import Aig
aig = Aig()
x1 = aig.create_pi()
x2 = aig.create_pi()
f_and = aig.create_and(x1, x2)
f_or = aig.create_or(x1, x2)
aig.create_po(f_and)
aig.create_po(f_or)
print(f"AIG Size: {aig.size()}")
Iterating over AIG Nodes
You can iterate over all nodes in the AIG, or specific subsets like the primary inputs or only logic nodes (gates).
for node in aig.nodes():
print(f"Node: {node}")
for pi in aig.pis():
print(f"Primary Input: {pi}")
for gate in aig.gates():
print(f"Gate: {gate}")
n_and = aig.get_node(f_and)
for fanin in aig.fanins(n_and):
print(f"Fanin of {n_and}: {fanin}")
Depth and Level Computation
You can compute the depth of the AIG network and the level of each node. Depth information is useful for estimating the
critical path delay of a respective circuit.
from aigverse import DepthAig
depth_aig = DepthAig(aig)
print(f"Depth: {depth_aig.num_levels()}")
for node in aig.nodes():
print(f"Level of {node}: {depth_aig.level(node)}")
Logic Optimization
You can optimize AIGs using various algorithms. For example, you can perform resubstitution to simplify logic using
shared divisors. Similarly, refactoring collapses maximmal fanout-free cones (MFFCs) into truth tables and resynthesizes
them into new structures. Cut rewriting optimizes the AIG by replacing cuts with improved ones from a pre-computed NPN
database.
from aigverse import aig_resubstitution, sop_refactoring, aig_cut_rewriting
aig_clone = aig.clone()
for optimization in [aig_resubstitution, sop_refactoring, aig_cut_rewriting]:
optimization(aig)
print(f"Original AIG Size: {aig_clone.size()}")
print(f"Optimized AIG Size: {aig.size()}")
Equivalence Checking
Equivalence of AIGs (e.g., after optimization) can be checked using SAT-based equivalence checking.
from aigverse import equivalence_checking
equiv = equivalence_checking(aig1, aig2)
if equiv:
print("AIGs are equivalent!")
else:
print("AIGs are NOT equivalent!")
AIGER Files
You can read and write (ASCII) AIGER files.
Parsing
from aigverse import read_aiger_into_aig, read_ascii_aiger_into_aig
aig1 = read_aiger_into_aig("example.aig")
aig2 = read_ascii_aiger_into_aig("example.aag")
print(f"AIG Size: {aig1.size()}")
print(f"AIG Size: {aig2.size()}")
Writing
from aigverse import write_aiger
write_aiger(aig, "example.aig")
Exporting Edge Lists
You can export the AIG as an edge list, which is useful for integration with graph libraries like NetworkX.
from aigverse import to_edge_list
edges = to_edge_list(aig)
print(edges)
edges = [(e.source, e.target, e.weight) for e in edges]
Truth Tables
Small Boolean functions can be efficiently represented using truth tables. aigverse
enables the creation and
manipulation of truth tables by wrapping a portion of the kitty library.
Creation
from aigverse import TruthTable
tt = TruthTable(3)
tt.create_from_hex_string("e8")
Manipulation
for i in range(tt.num_bits()):
print(f"Flipping bit {int(tt.get_bit(i))}")
tt.flip_bit(i)
print(tt.to_binary())
tt.clear()
print(tt.is_const0())
Symbolic Simulation of AIGs
from aigverse import simulate
tts = simulate(aig)
for i, tt in enumerate(tts):
print(f"PO{i}: {tt.to_binary()}")
Exporting as Lists of Lists
For some machine learning applications, it may be useful to export the truth table as a list of lists.
tt_list = [[int(tt.get_bit(i)) for i in range(tt.num_bits())] for tt in tts]
Contributing
Contributions are welcome! If you'd like to contribute to aigverse
, please submit a pull request or open an issue. I
appreciate feedback and suggestions for improving the library.
License
aigverse
is available under the MIT License.